1. Field of the Invention
The present invention generally relates to a magnetic core memory drive system and, more particularly, to a read and write drive system for a 21/2D magnetic core memory.
2. Description of the Prior Art
The advantages of a 21/2D coincident current magnetic core memory, as compared with a 2D or 3D memory, are well known. In such a 21/2D memory, magnetic cores used to store the corresponding bit, e.g., the least significant bit, of all the multibit words are threaded by a plurality of word lines and a plurality of bit lines. One word line and one bit line are threaded through each core. The bit lines threaded through the cores storing the same bit of all the words are interconnected to form a matrix of a plurality of groups of bit lines with an equal number of bit lines per group. Typically, the number of groups and the bit lines per group are powers of two. Different cores storing different bits of the same word are threaded by the same word line and by corresponding bit lines of the different bit line matrices. For example, a 21/2D memory of a capacity of 8192 words, with 512 word lines incudes 16 bit lines per word bit. The 16 bit lines are arranged in a matrix of M groups each of N bit lines where M.sup.. N = 16. Assuming that each word is of 8 bits, the memory includes 8 bit line matrices, each of 16 bit lines.
Herebefore the drive circuitry associated with each word bit includes 2(M+N) separate switches, e.g., M separate write drive switches, M separate read sink switches, N separate read drive switches and N separate write sink switches. These switches are used to drive through a selected bit line 1/2 read drive current in one direction during a read operation, and 1/2 write drive current in the opposite direction during a write operation, if the bit of the particular addressed word is to store a binary 1. Generally, M and N are chosen so as to minimize the total number of required switches per word bit. Where M.sup.. N = 16, M = N = 4, so that the total number of switches is 2(M+N) = 2.sup.. 8 = 16. Clearly, if the 16 bit lines were divided into two groups (M=2) with eight (N=8) bit lines per group the total number of required switches would be 2(M+N) = 2.sup.. 10 = 20.
It is apparent that in order to minimize the memory cost and reduce its complexity it is highly desirable to be able to reduce the total number of required switches for the entire memory.